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IR3710MTRPBF
DESIGN EXAMPLE
Δ I =
1.1 V ? ( 21 V - 1.1 V )
21 V ? 0.56u H ? 300K Hz
= 6.2 A
1 ? 6.2 A ?
1.1 V
Design Criteria:
Input Voltage, V IN , = 6V to 21V
Output Voltage, V OUT = 1.1V
Switching Frequency, F S = 300KHz
Inductor Ripple Current, Δ I = 5A
Maximum Output Current, I OUT = 20A
Over Current Trip, I OC = 30A
Overshoot Allowance, V OS = V OUT + 150mV
Undershoot Allowance, V DROP = 150mV
Find R FF :
Choose input capacitor:
2
I IN_RMS = 20 A ? ? 1 + ? ? ? = 4.7 A
21 V 3 ? 20 A ?
A 10uF (ECJ3YB1E106M) from Panasonic
manufacture has 6Arms at 300KHz. Due to the
chemistry of multilayer ceramic capacitors, the
capacitance varies over temperature and operating
voltage both of AC and DC. Two (2) of 10uF are
recommended. In practical solution, one (1) of 1uF is
R FF =
1.1 V
1 V ? 20 pF ? 300K Hz
= 183 K Ω
required along with 2x10uF. The purposes of 1uF are
to suppress the switching noise and deliver a high
frequency current.
Pick 182K ? for 1% standard resistor
Find R SET :
Choose output capacitor:
To meet the undershoot specification, select a set of
output capacitor which has an equivalent of 7.5m ?
R SET =
1.3 ? 3m Ω ? 30 A
20 μ A
= 5.85K Ω
(150mV/20A). To meet the overshoot specification,
equation 15 will be use to calculate the minimum
output capacitance. As a result, 516uF will be
1.3 factor is base on R DSON of lower MOSFET
increase over the temperature. Therefore, pick 5.9K
for 1% standard resistor.
Find resistor divider for V OUT = 1.1V:
needed. Combine those two requirements, one can
choose a set of output capacitor bank from
manufactures such as SP-Cap (Specialty Polymer
Capacitor) from Panasonic or POSCAP from Sanyo.
Two (2) of 270uF (EEFUD0D271XR) from Panasonic
are recommended. This capacitor has 12m ? ESR
V FB =
R 2
R 2 + R 1
? V OUT = 0.5 V
which leaves margin for voltage drop of ESL during
load step up. The typical ESL for this capacitor is
around 2nH.
R 2 = 8.45K ? , R 1 = 10K ? for 1% standard resistor
Choose the soft start capacitor:
Once the soft start time has chosen such as 100uS to
reach to the reference voltage, a 2.2nF for C SS is
used to meet 100uS.
Choose inductor to meet design specification:
LAYOUT RECOMMENDATION
Bypass Capacitor:
One 1uF high quality ceramic capacitor is
recommended to be placed as near VCC pin as
possible. Other end of capacitor can be via or directly
connect to GND plane. Use a GND plane not a thin
trace to GND pin because this thin trace has higher
impedance compare to GND plane. A 1uF is
recommended for both V5 and PVCC and repeat the
L =
V OUT ? ( V IN ? V OUT )
V IN ? Δ I ? F s
=
1.1 V ? ( 21 V - 1.1 V )
21 V ? 5 A ? 300K Hz
= 0.7u H
layout procedure above for those signals.
Charge Pump:
It is recommended to place D1, D2 and C2 as close
to the CPO and PVCC pins as possible. If those
Choose the inductor with lowest DCR and AC power
loss as possible to increase the overall system
efficiency. For instance, choose FDUE1250-R56M
from TOKO manufacture. The inductance of this part
is 0.56uH and has 0.82m ? DCR. The core loss for
this inductor is 0.41W and 0.41W for DCR. Ripple
current needs to recalculate with a chosen inductor.
components can not placed on the same layer as
IR3710, a minimum of two (2) vias need for the
connection of C2 and CPO pin and the connection of
D2 and PVCC.
Boot Circuit:
C BOOT needs to place near BOOT and PHASE pins to
reduce the impedance during the turn on of the upper
MOSFET. D BOOT does not need to be close to C BOOT
because the average current to charge C BOOT is small
during the on time of lower MOSFET.
Page 15 of 20
www.irf.com
IR Confidential
4/26/10
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